The concept of the discrete linear transform (e.g. Fourier Transform, Chirp-Z Transform, Hartley Transform) is central to the signal processing industry. Discrete (i.e. sampled) signals are represented by the vector V EQU v=(V.sub.1, . . . V.sub.j, . . . V.sub.N)
whose elements (N in all) are the temporal or spatial samples of the input signal. The discrete linear transform (DLT) is performed by computing a vector-matrix multiplication, where the input vector contains the input signal and the resultant vector contains the transformed signal. The square matrix (N by N) contains the transform information--for example, in a Discrete Cosine Transform, the matrix is simply a cosine matrix: EQU W.sub.ij =cos (i*j*.pi./N)
and the calculation is: EQU U.sub.i =.SIGMA..sub.j W.sub.ij *V.sub.j
All DLT's can be represented in the form of the simple vector-matrix multiplication above. In practice, however, implementations of DLT's often take advantage of the symmetry available in the W matrix to reduce the number of multiply-accumulate (MAC) operations (e.g. the FFT algorithm). These symmetries are not available in the general DLT case, giving the FFT and similar algoriths the advantage in terms of total MAC's. General DLT hardware (i.e. a vector-matrix multiplier), however, offers a significant flexibility advantage over a dedicated piece of transform hardware optimized for a single algorithm. A need thus exists for a highly parallel DLT signal processing device useful for implementing general DLT's.
Recently, the field of neural networks (NN) has experienced intensive development. NN theories provide a framework from which general nonlinear transforms can be built. The computation typically involves a vector-matrix multiplication (the bulk of the calculation) and the application of a nonlinearity. Current efforts of NN simulation typically rely on sequential hardware to calculate the vector-matrix multiplication, whereas the task is inherently parallel. Thus it can be seen that it would be highly advantageous to have a signal processing device which provides a high speed, high accuracy method of providing vector-matrix multiplication.
One such device is described in an article by Agranat and Yariv, two of the inventors herein, entitled "Semi-Parallel Microelectronic Implementation of Neural Network Models Using CCD Technology" Electronics Letters, Volume 23, Number 11, Pages 580-581, May 21, 1987. A vector-matrix multiplier using the nondestructive readout phase of charge-injection devices (CID's) is disclosed in another article by Agranat, Neugebauer and Yariv, entitled "Parallel Optoelectronic Realization of Neural Network Models Usinq CID Technology", Applied Optics, Volume 27, Page 4354, Nov. 1, 1988. The CCD implementation of a vector-matrix multiplier as described in the earlier of the two above-identified articles, contains 65,536 analog matrix elements which can be multiplied by a 256 length vector in a semi-parallel fashion at a rate of roughly 10.sup.9 multiply-accumulate's per second. The second of the above noted articles describes a truly parallel vector-matrix multiplication scheme. This scheme relies on the nondestructive sensing portion of charge-injection device technology in which each pixel of an N.times.N two-dimensional CID detector array contains charge in direct proportion to the corresponding values of the interaction matrix W.
A CCD implementation for carrying out a vector-matrix product algorithm is disclosed in an article entitled A 100MS 16-Point CCD Cosine Transform Processor by Chiang et al. at page 306 of the digest of technical papers of the 1987 IEEE International Solid-State Circuits Conference. Unfortunately, this implementation is slower and requires more semiconductor "real estate" than would be needed in a practical DLT or other signal processing application. Furthermore, the Chiang et al. scheme is severely limited in its application to general signal processing uses.
A need still exists therefore for practical system integration of such a high speed charge domain signal processor that is faster, larger in scale, has more general application and which provides digital input/output functions so that such signal processors can operate with standard digital memories and communication methods in high speed, high accuracy implementation of vector-matrix multipliers in DLT applications, neural networks and in other signal processing functions.